Senior Design Engineer (High Performance AI Chips)

Located in the South San Francisco Bay Area, we are a Semiconductor Startup with over $70M in funding that's on pace to secure our Series C in the coming months! We are building a universal processor that combines the functionality of a CPU, GPU, and TPU into one handling some of the largest AI and Machine Learning workloads around.

We are seeking Senior Design Engineers who are local or willing to relocate to the San Francisco Bay area that have experience in at least once of the following (in order of urgency):

• HW Memory Subsystem Design (advanced DRAM control block)
• High Speed L2 Cache (high speed and low power processor pipeline designs / ASICs / SoCs and multi-core designs)
• Digital Design Engineers (ARM and x86 and multicore processor designs, FPGA, PCIe, Ethernet / 100G+, DDR4)
• CPU Execution Unit (ALU logic design)
• CPU Fetch Unit (branch prediction algorithms / instruction fetch design of high performance microprocessors)
• Serial Interfaces (High Speed Coherent Interconnect - blocks include Boot logic, Serial Interfaces, and debug logic / integration and debug of APB, AHB, and AXI interconnects)
• PCIe Interfaces (build infrastructure to support PCIe during FPGA emulation and bringup)

Benefits

• Competitive salary and benefits package + stock options
• Relocation assistance in form of sign-on bonus
• Opportunities for professional development and advancement
• International environment and further career progression
• Getting in touch with bleeding edge technology
• Flexible working hours with work-life balance
• Collaborative and supportive work environment
• Ability to work from home (must reside in the Bay Area or Las Vegas to meet with the team as needed)