Senior Engineer, Package Design
Apply NowCompany: Metaoption
Location: Milpitas, CA 95035
Description:
Senior Engineer, Package Design
We need a Sr. candidate 7 + years of experience in Package design, with a mix of Si and Pi. Someone that has held a position of ownership on multiple levels of ASIC Package Design on next generation chips. Pre-silicon, not at manufacturing level.
Responsibilities
The Package substrate design focus on signal and power integrities analyses as well as routing analyses. You will be reporting to the Director of Package Design (USA) and working very closely with Package design team in our parent company's headquarters in Japan and Marketing and Engineering teams located in our Milpitas office during pre/post sales process.
This position requires a broad knowledge of package technology and design. Successful candidates will have a deep understanding and experience in the following areas: high performance build-up substrates, flip chip assembly or 2.5D packaging. Knowledge and experience in extracting/simulating package designs for Signal and Power integrities using tools such as HFSS, and/or ADS tools.
Education
Bachelor's degree in Electrical Engineering, or other semiconductor packaging related discipline
MS is preferred
Required Experience and Skills
8 to 10 years of experience in semiconductor packaging design, modeling, extraction, and simulations
Record of success in cross-functional team environment
Good experience with Signal and power integrity tools for package level modeling/extraction/simulation
Ability to work with Package Layout engineers.
Strong presentation and communication skills
Preferred Experience and Skills
Hands on package design; high-speed Signa integrity and Power integrity and package decoupling caps optimizations, combined package and PCB Signal integrity and Power integrity Characterizations, impedance verification, high frequency s-parameters extraction, Hspice model, package Hspice and RLC model extraction and designs
Hands on high-speed package and PCB design for: high-speed Serdes 112 Gbps, PCIeX5 and 6, LPDDR4,5, Ethernet 25 GBps, power aware SI/PI analysis, up to 40 GHZ s-parameters extraction and verification
Packaging+PCB high-speed interconnections timing analyses, eye-diagram and jitter budgeting calculation following the LPDDR JEDEC spec, or other highs-speed frequency domain s-parameters extraction following the base Spec of high-speed interconnect
Hands on PCB design; SI, PI analyses, decoupling caps optimizations, SI and PI Characterization and extractions, impedance verification, s-parameters verifications with lab measurements, Hspice model, PCB RLC model extraction and designs
Packaging routing analyst, trace impedance analyses and package layout bump to ball analyses
Package material characterization frequency dependent model; skin effects, smoothness, roughness, dielectric loss and dielectric constant
PCB material characterization frequency dependent; routing degree of freedom
Time domain analyses and jitter budgeting for PCIe2/3/4/5, Serdes 112 GBps, Ethernet 25 Gbps, LPDDR4/5X MIPI, high-speed frequency signaling
Time domain analyses and budgeting model for LPDDR 3/4/5, LPDDRX 3/4/5/6
Bathtub curve and BER analyses of high speed signaling
DDR frequency and time domains model and jitter analyses and path findings to improve package and PCB layout and improve high-speed interconnections
Clk jitter analyses, routing, clk tree analyses
Simulating multi-physics electro-thermal analysis
Collateral packaging manufacturing and assembly rules
Chip and package Reliability analyses
Die+Pkg+pcb PDN model time and frequency, Impedance profile, AC droop, DC drop DC, etc.
IR drop, and CPM (chip power model) die model using Redhawk and other tolls
Core PI: simulation capability, tool/flow and past experience on measurement capability, lab tool set up.
We need a Sr. candidate 7 + years of experience in Package design, with a mix of Si and Pi. Someone that has held a position of ownership on multiple levels of ASIC Package Design on next generation chips. Pre-silicon, not at manufacturing level.
Responsibilities
The Package substrate design focus on signal and power integrities analyses as well as routing analyses. You will be reporting to the Director of Package Design (USA) and working very closely with Package design team in our parent company's headquarters in Japan and Marketing and Engineering teams located in our Milpitas office during pre/post sales process.
This position requires a broad knowledge of package technology and design. Successful candidates will have a deep understanding and experience in the following areas: high performance build-up substrates, flip chip assembly or 2.5D packaging. Knowledge and experience in extracting/simulating package designs for Signal and Power integrities using tools such as HFSS, and/or ADS tools.
Education
Bachelor's degree in Electrical Engineering, or other semiconductor packaging related discipline
MS is preferred
Required Experience and Skills
8 to 10 years of experience in semiconductor packaging design, modeling, extraction, and simulations
Record of success in cross-functional team environment
Good experience with Signal and power integrity tools for package level modeling/extraction/simulation
Ability to work with Package Layout engineers.
Strong presentation and communication skills
Preferred Experience and Skills
Hands on package design; high-speed Signa integrity and Power integrity and package decoupling caps optimizations, combined package and PCB Signal integrity and Power integrity Characterizations, impedance verification, high frequency s-parameters extraction, Hspice model, package Hspice and RLC model extraction and designs
Hands on high-speed package and PCB design for: high-speed Serdes 112 Gbps, PCIeX5 and 6, LPDDR4,5, Ethernet 25 GBps, power aware SI/PI analysis, up to 40 GHZ s-parameters extraction and verification
Packaging+PCB high-speed interconnections timing analyses, eye-diagram and jitter budgeting calculation following the LPDDR JEDEC spec, or other highs-speed frequency domain s-parameters extraction following the base Spec of high-speed interconnect
Hands on PCB design; SI, PI analyses, decoupling caps optimizations, SI and PI Characterization and extractions, impedance verification, s-parameters verifications with lab measurements, Hspice model, PCB RLC model extraction and designs
Packaging routing analyst, trace impedance analyses and package layout bump to ball analyses
Package material characterization frequency dependent model; skin effects, smoothness, roughness, dielectric loss and dielectric constant
PCB material characterization frequency dependent; routing degree of freedom
Time domain analyses and jitter budgeting for PCIe2/3/4/5, Serdes 112 GBps, Ethernet 25 Gbps, LPDDR4/5X MIPI, high-speed frequency signaling
Time domain analyses and budgeting model for LPDDR 3/4/5, LPDDRX 3/4/5/6
Bathtub curve and BER analyses of high speed signaling
DDR frequency and time domains model and jitter analyses and path findings to improve package and PCB layout and improve high-speed interconnections
Clk jitter analyses, routing, clk tree analyses
Simulating multi-physics electro-thermal analysis
Collateral packaging manufacturing and assembly rules
Chip and package Reliability analyses
Die+Pkg+pcb PDN model time and frequency, Impedance profile, AC droop, DC drop DC, etc.
IR drop, and CPM (chip power model) die model using Redhawk and other tolls
Core PI: simulation capability, tool/flow and past experience on measurement capability, lab tool set up.