Silicon Physical Design Engineer II

Iron Systems is an innovative, customer-focused provider of custom-built computing infrastructure platforms such as network servers, storage, OEM/ODM appliances & embedded systems. For more than 15 years, customer have trusted us for our innovative problem solving combined with holistic design, engineering, manufacturing, logistic and global support services.

Job Title: Silicon Physical Design Engineer II
Location: US - CA - Sunnyvale

Job Description:

• Strong understanding in the analog layout design
• Experience with block level layout floor planning and execution
• Experience working with most EDA tools like virtuoso layout editor, Calibre DRC & LVS, Totem/Voltus

Duties:

• Design complex layout for mixed signal and analog circuit in deep sub-micron CMOS technologies
• Work with circuit design to floor plan and complete the layout
• Run and fix complete set of physical design verification and reliability verification
• Review and analyze the layout with the circuit designers
• Layout integration and final verification for tape out

Must Have:

• 5 years of relevant analog mixed signal layout design experience
• Experience in running physical verification such as DRC, LVS, ERC, LVSERC, Antenna, Density, and LUP
• Experience in Block-level and chip level layout execution
• Experience in analog layout floor planning

Wish List/ Nice to Have:

• skill programming experience

Education

• Bachelor degree in Electrical/Computer Engineering or Computer Science is a plus

Must-have HARD skills:

• Analog and mixed signal design experiences
• Virtuoso and calibre

Good to have skills:

• Top down and bottom-up floor plan experiences
• Full chip integration experiences
• EMIR, DFM, ERC, PERC experiences

Story Behind the Need - Business Group & Key Projects:

• To support AMS research program in AR

Compelling story:

• Plans to extend with good performance
• Excitement to get explore and learn about ARVR technology
• Opportunity to work on advance process nodes from TSMC, GF, and Samsung

Typical Day in the Role:

• IP layout development daily

Mandatory Skills

5 years of relevant analog mixed signal layout design experience Experience in running physical verification such as DRC, LVS, ERC, LVSERC, Antenna, Density, and LUP