Digital ASIC Design and Verification

If you are tired of feeling stuck in your "cube farm" then this company is for you!

We have partnered with a growing, privately held technology company. As they continue to fuel their growth our client is looking for a Digital ASIC Design and Verification Engineer. Their team is built around 20 years of expertise in delivering connectivity Silicon IP solutions which has led to the most power efficient and high-performance solution available on the market. They are interested in driven and talented individuals who have a passion for chip development.

Responsibilities:

• Create and implement block, chip & system-level Design Verification Plan from ASIC concept to silicon
• Design / Implement simulation testbenches, reference models and bus-functional models, assertions / infrastructure in System Verilog, C/C++, SystemC and Python
• Work closely with rest of ASIC design,and SW teams to implement the SOC
• Implement/maintain verification infrastructures, tools, and flows

Requirements

• 4+ years of design verification experience on complex ASIC's
• Strong System Verilog, UVM and ASIC debugging skills on a variety of platforms and simulators (VCS)
• Strong C/C++ programming and scripting (e.g. Makefiles, Python, Perl, tcl) skills
• Ability to innovate, adapt and work independently and in a team in a fast-paced environment
• Experience with PCIe, Ethernet and high speed data communication products

This is the perfect opportunity to join a team of leaders in the industry who are invested in your growth and development.

How to Apply?
All qualified and interested applicants can apply directly to Aaron Ravensbergen by sending an email with attached resume to [redacted] . You may also apply directly on our website at www.talentlab.com . Although we thank all applicants for their interest, only those in consideration will be contacted.