Design Verification Engineer ( Remote)
Apply NowCompany: Encore Semi LLC
Location: Dallas, TX 75217
Description:
About the Team:
Join the growing Encore Semi Front-End Development team to collaborate with customers to design, verify and enable various subsystems and full-chip for current and next generation ASICs and SOCs. Building on your background of SV/UVM-based Design Verification, you would join a team integrating internal and 3 rd party IPs into SOCs and verifying overall functional correctness.
About the Project:
As a senior member of an ASIC development team, you will be responsible for building a Functional Verification environment for new designs incorporating internally developed RTL and 3 rd party IPs. You will leverage your SV/UVM experience verify interfaces and interconnect. If you have SOC Integration Verification experience implementing SV/UVM environments and stimulus, directing random stimulus and deploying a coverage-based approach, joining the Encore Semi Verification team could be for you.
Minimum Qualifications:
Preferred Qualifications:
Education Requirements:
Join the growing Encore Semi Front-End Development team to collaborate with customers to design, verify and enable various subsystems and full-chip for current and next generation ASICs and SOCs. Building on your background of SV/UVM-based Design Verification, you would join a team integrating internal and 3 rd party IPs into SOCs and verifying overall functional correctness.
About the Project:
As a senior member of an ASIC development team, you will be responsible for building a Functional Verification environment for new designs incorporating internally developed RTL and 3 rd party IPs. You will leverage your SV/UVM experience verify interfaces and interconnect. If you have SOC Integration Verification experience implementing SV/UVM environments and stimulus, directing random stimulus and deploying a coverage-based approach, joining the Encore Semi Verification team could be for you.
Minimum Qualifications:
- Experience should include creating Verification Plans from the Microarchitecture Specifications and ability to understand Verilog RTL.
- SV/UVM methodology expertise to create Verification environments and drive Functional Verification including the incorporation of internal IPs and 3 rd party IPs from different suppliers.
- Experience debugging RTL simulations including waveform-based debugging.
- 5+ years of Design Verification experience including working with RTL Developers.
- Knowledge of high-speed interfaces such as PCIe, DDR, and Ethernet.
Preferred Qualifications:
- Verification experience focused in any of the following areas of ASIC/SOC designs:
- Processor cores
- DSPs
- General control logic
- Experience developing Verification methodologies or environments incorporating various levels of coverage but, most importantly, functional coverage (as opposed to code or statement coverage).
- Experience with industry standard EDA tools.
Education Requirements:
- Required: Bachelor's, Electrical Engineering
- Preferred: Master's, Electrical Engineering