Fabric Design and Verification Engineers
Apply NowCompany: ACL Digital
Location: San Jose, CA 95123
Description:
Role Overview:
We are seeking a skilled Fabric Design and Verification Engineer to lead the verification of a high-performance fabric, implemented as a multiple-tile array(32,64,128, 144, 172). Each tile supports three operational flavors (load-store, complex arithmetic, and basic integer) and communicates with other tiles and the top-level system via an on-chip network. The successful candidate will develop advanced verification environments, ensure functional correctness, and optimize the design for performance and reliability.
Key Responsibilities:
Design and Development:
* Collaborate with the architecture team to understand fabric and tile-level specifications.
* Design Verification Environment for the on-chip interconnect and tile operations (load-store, arithmetic, and integer).
* Implement and optimize routing algorithms and data flow mechanisms for the mesh fabric.
Verification and Validation:
* Develop and execute UVM-based testbenches for fabric and tile verification.
* Design and implement tests for intra-tile, inter-tile, and top-level communication.
* Ensure correct programming and execution of load-store, arithmetic, and integer operations within each tile.
* Validate communication protocols and data integrity across the on-chip network.
* Perform corner-case, stress, and fault injection testing to ensure robustness.
Debug and Analysis:
* Analyze RTL and simulation failures, identify root causes, and drive fixes.
* Utilize advanced debug tools for transaction-level and waveform analysis.
* Evaluate performance metrics, including latency, bandwidth, and power consumption.
Coverage and Reporting:
* Develop and track functional and code coverage metrics.
* Implement cross-coverage to capture interaction between tile flavors and transaction types.
* Document verification plans, test results, and coverage closure reports.
Required Qualifications:
* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
* 9+ years of experience in RTL design and verification.
* Proficiency in SystemVerilog and UVM methodology.
* Experience with mesh-based interconnects or large-scale tiled architectures.
* Strong understanding of load-store operations, arithmetic logic, and integer processing.
* Knowledge of on-chip networks, including routing protocols and traffic management.
* Familiarity with simulation tools (e.g., VCS, Questa, Xcelium) and waveform analysis.
Preferred Skills:
* Experience with formal verification and assertion-based methods.
* Knowledge of cache coherence protocols and memory consistency models.
* Scripting proficiency (Python, Perl, or TCL) for automation.
* Experience in performance modeling and bottleneck analysis.
* Strong documentation and communication skills.
We are seeking a skilled Fabric Design and Verification Engineer to lead the verification of a high-performance fabric, implemented as a multiple-tile array(32,64,128, 144, 172). Each tile supports three operational flavors (load-store, complex arithmetic, and basic integer) and communicates with other tiles and the top-level system via an on-chip network. The successful candidate will develop advanced verification environments, ensure functional correctness, and optimize the design for performance and reliability.
Key Responsibilities:
Design and Development:
* Collaborate with the architecture team to understand fabric and tile-level specifications.
* Design Verification Environment for the on-chip interconnect and tile operations (load-store, arithmetic, and integer).
* Implement and optimize routing algorithms and data flow mechanisms for the mesh fabric.
Verification and Validation:
* Develop and execute UVM-based testbenches for fabric and tile verification.
* Design and implement tests for intra-tile, inter-tile, and top-level communication.
* Ensure correct programming and execution of load-store, arithmetic, and integer operations within each tile.
* Validate communication protocols and data integrity across the on-chip network.
* Perform corner-case, stress, and fault injection testing to ensure robustness.
Debug and Analysis:
* Analyze RTL and simulation failures, identify root causes, and drive fixes.
* Utilize advanced debug tools for transaction-level and waveform analysis.
* Evaluate performance metrics, including latency, bandwidth, and power consumption.
Coverage and Reporting:
* Develop and track functional and code coverage metrics.
* Implement cross-coverage to capture interaction between tile flavors and transaction types.
* Document verification plans, test results, and coverage closure reports.
Required Qualifications:
* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
* 9+ years of experience in RTL design and verification.
* Proficiency in SystemVerilog and UVM methodology.
* Experience with mesh-based interconnects or large-scale tiled architectures.
* Strong understanding of load-store operations, arithmetic logic, and integer processing.
* Knowledge of on-chip networks, including routing protocols and traffic management.
* Familiarity with simulation tools (e.g., VCS, Questa, Xcelium) and waveform analysis.
Preferred Skills:
* Experience with formal verification and assertion-based methods.
* Knowledge of cache coherence protocols and memory consistency models.
* Scripting proficiency (Python, Perl, or TCL) for automation.
* Experience in performance modeling and bottleneck analysis.
* Strong documentation and communication skills.