Principal Design Verification Engineer
Apply NowCompany: Marvell Technology
Location: Santa Clara, CA 95051
Description:
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As part of the Design Verification Team at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers' specifications whether they're a major telecom organization or automotive company, etc.
What You Can Expect
In this role, you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development.
Activities may include:
Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.
Developing tests and tuning the environment to achieve coverage goals. Debugging failures and working with designers to resolve issues.
Verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs.
Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment.
Unit and regression testing of software tools.
What We're Looking For
Requirements
Other Skills:
Expected Base Pay Range (USD)
146,850 - 220,000, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
#LI-TM1
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As part of the Design Verification Team at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers' specifications whether they're a major telecom organization or automotive company, etc.
What You Can Expect
In this role, you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development.
Activities may include:
Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.
Developing tests and tuning the environment to achieve coverage goals. Debugging failures and working with designers to resolve issues.
Verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs.
Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment.
Unit and regression testing of software tools.
What We're Looking For
Requirements
- Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience. Or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5+ years of experience.
- Strong background in PCIe protocols and applications with at least 3 years of experience
- Strong background in SOC verification and test bench development using UVM, System Verilog, C/C++, and DPI.
- Strong verification skills, understanding of methodology (object oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations, data structure).
Other Skills:
- Must have effective interpersonal and teamwork skills.
- Participate in problem solving and quality improvement activities.
- Demonstrate initiative and a bias for thoughtful action.
- Grounded, detail-oriented, always backs up ideas with facts.
- Must have the ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.
Expected Base Pay Range (USD)
146,850 - 220,000, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
#LI-TM1