Design Verification Engineer - SoC Infrastructure

Overview

We're seeking a passionate Verification Engineer with a strong background in UVM-based verification and experience in working with complex ARM/RISC-based SOCs to join our dynamic team.

Looking for candidates in Mountain View, CA | El Segundo, CA | Austin, TX

Long term Contract

Responsibilities

As a Verification Engineer with expertise in subsystems and SoCs, you will be responsible for verifying the functional correctness of RTL for infrastructure SOCs. You'll collaborate closely with the project team to understand subsystem architecture, review design specifications, and develop a comprehensive verification strategy. Your key responsibilities will include planning verification activities, delivering high-quality SoC RTL within specified timelines, and leading the verification team in crafting test plans, developing testbenches, and debugging test failures.

Requirements

• Experience with SystemVerilog and verification methodologies (UVM)
• UVM From Scratch
• Solid understanding of digital hardware design and Verilog HDL.
• Detailed understanding and experience of current verification strategies for sophisticated SOC development, including software-based techniques.
• Good knowledge of test plan creation and tracking.

Nice To Have Skills & Experience:

• Experience with ARM-based designs and/or RISC-V-based SOC.
• Experience leading teams or projects.
• Experience or knowledge in clock domain crossing verification, power-aware verification, and development of complex SOCs on emulation platforms.
• Experience working with emulators and debugging complex SOC designs.