Senior Design Verification Engineer
Apply NowCompany: Cynet Systems
Location: Ottawa, ON K1A 0A5
Description:
Job Description:
Responsibilities:
Responsibilities:
- Develop/Maintain tests for functional verification with UVM verification at the subsystem level.
- Build testbench components to support the next generation IP.
- Maintain or improve current test libraries to support IP level testing.
- Technically lead IPs in Control Fabric.
- Have exposure to AXI protocol and Bootcode Verification.
- Provide technical support to other teams.
- 5+ years' experience required.
- Good at C/C++.
- Good at SV and UVM.
- Good scripting knowledge in Perl, Ruby and Makefile.
- Familiarity with System Verilog and modern verification libraries like UVM.
- Bachelors (required) or Masters degree in computer engineering/Electrical Engineering.