Senior SoC Power Architect, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 5 years of experience with computer architecture concepts, including microarchitecture, cache hierarchy, pipelining, and memory subsystems.
• 5 years of experience in SoC power management or low power design/methodology.
• Experience with Application-Specific Integrated Circuit (ASIC) low power flows and power management concepts.

Preferred qualifications:

• Master's Degree or PhD in Electronics or Computer Engineering/Science, with an emphasis on computer architecture, performance and power analysis.
• 8 years of experience in SoC power management or low power design/methodology.
• Experience in CPU power in mobile SoCs from CPU architecture and design to schedulers, governors and post-silicon tuning for power and performance.
• Experience with ASIC power modeling/estimation, defining power targets, power roll-ups, power/voltage domains design and low power architectures/optimization techniques.
• Experience with software and architectural design decisions on system power and thermal behavior.
• Experience with ASIC design flows from concept to post-silicon.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $156,000-$229,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Define and drive low power solutions for Google System on a Chips (SoC) to optimize Power-Performance-Area (PPA) under peak current and thermal constraints with a focus on the CPU subsystem.
• Define power key performance indicators and SoC/IP-level power targets, guide architecture, design and implementation to achieve power targets, create power models, perform power roll ups and track power throughout the design cycle.
• Propose and drive power optimizations, both hardware and software, throughout the design process from concept to mass productization.
• Drive power-performance trade-off analysis for engineering reviews and product road-map decisions.
• Perform post-silicon characterization and productization of power features.