PLL (Phase-Locked Loop) Analog/Mixed Signal Designer - San Jose
Apply NowCompany: TikTok
Location: San Jose, CA 95123
Description:
Responsibilities
About the team:
This team is at the forefront of technological innovation, specializing in the design, development, and production of CPUs for ByteDance data center servers. Leveraging a team of highly skilled engineers, researchers, and experts, the unit focuses on creating high-performance, energy-efficient, and reliable chips that power a wide range of electronic devices and systems.
Responsibilities
- Design and model PLL circuits at high speed or above at both system and circuit levels.
- Develop analog circuits, including VCOs (high speed, ring preferred and/or LC), charge pumps, loop filters, voltage regulators, PFDs, and dividers.
- Custom design circuits in deep-submicron and FINFET CMOS technologies.
- Create high-speed circuits such as dividers and clock distribution paths.
- Perform schematic entry and SPICE simulation of custom circuits.
- Collaborate with cross-functional teams to optimize design performance and reliability.
- Supervise layout engineers for circuit layout and conduct post-layout simulations with LPE fixes.
Qualifications
Minimum Qualifications:
- MS in Electrical Engineering or a related field.
- Hands-on experience with PLL design.
Preferred Qualifications:
- 5 years of experience in analog circuit design.
- MS/PhD in Electrical Engineering or a related field with 5 years of experience.
- Direct experience in PLL design.
- In-depth knowledge of PLL loop operation and design.
- Experience in designing PLL circuit components such as VCOs (high speed, ring preferred and/or LC), charge pumps, loop filters, regulators, PFDs, and dividers.
- Proficiency in designing high-speed circuits and working with deep-submicron and FINFET CMOS technologies.
- Experience with schematic entry in Cadence Custom Designer or similar tools.
- Knowledge of digital timing in PrimeTime and/or Nanotime is a plus.
#LI-MZ3
About the team:
This team is at the forefront of technological innovation, specializing in the design, development, and production of CPUs for ByteDance data center servers. Leveraging a team of highly skilled engineers, researchers, and experts, the unit focuses on creating high-performance, energy-efficient, and reliable chips that power a wide range of electronic devices and systems.
Responsibilities
- Design and model PLL circuits at high speed or above at both system and circuit levels.
- Develop analog circuits, including VCOs (high speed, ring preferred and/or LC), charge pumps, loop filters, voltage regulators, PFDs, and dividers.
- Custom design circuits in deep-submicron and FINFET CMOS technologies.
- Create high-speed circuits such as dividers and clock distribution paths.
- Perform schematic entry and SPICE simulation of custom circuits.
- Collaborate with cross-functional teams to optimize design performance and reliability.
- Supervise layout engineers for circuit layout and conduct post-layout simulations with LPE fixes.
Qualifications
Minimum Qualifications:
- MS in Electrical Engineering or a related field.
- Hands-on experience with PLL design.
Preferred Qualifications:
- 5 years of experience in analog circuit design.
- MS/PhD in Electrical Engineering or a related field with 5 years of experience.
- Direct experience in PLL design.
- In-depth knowledge of PLL loop operation and design.
- Experience in designing PLL circuit components such as VCOs (high speed, ring preferred and/or LC), charge pumps, loop filters, regulators, PFDs, and dividers.
- Proficiency in designing high-speed circuits and working with deep-submicron and FINFET CMOS technologies.
- Experience with schematic entry in Cadence Custom Designer or similar tools.
- Knowledge of digital timing in PrimeTime and/or Nanotime is a plus.
#LI-MZ3