Physical Design Engineer

Job Details:

Job Description:

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the links below.

Life at Intel

Diversity at Intel

This role is within Intel's Client Computing Group. CCG is a computing paradigm where services and data reside in scalable data centers, and those services and data can be accessed by any connected device over the Internet. Responsible for designing and optimizing processors, chipsets and other hardware for consumer devices while also working on the software ecosystem, including drivers and utilities that enhance user experience.

Your responsibilities may include but not be limited to:

• Performs physical design implementation of DDRIP designs with focus on Static Timing Analysis & Timing Closure.
• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis at the block level
• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to fix violations for current and future product architecture.
• Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, constraints debug, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
• Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

The Physical Design Engineer should possess the following attributes:

• Excellent written and verbal communication skills.
• Willingness to work effectively in a collaborative, cross-functional environment.
• Excellent problem-solving and debugging skills
• Ability to lead task forces to resolve problems

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

What we need to see (Minimum Qualifications):

Bachelor's degree in Electrical Engineering or related field with 4+ years of work experience OR Master's degree in Electrical Engineering or related field with 3+ years of work experience

3+ years of experience in the following:

- Experience in Block/Top Floor planning, Synthesis and PnR (preferably in complex Mixed-Signal blocks involving multiple analog blocks)
- Experience in Block/Top STA, Timing Closure, Constraints debug, ECO generation etc.
- Experience in debug of LVS, DRC and other layout verification flows.
- Experience in one or more of the follow industry standard tools (eg. Fusion Compiler, Primetime, Conformal etc.).
- Experience in one or more scripting languages (eg. TCL, Perl, Python etc.).

Preferred Qualifications:
MS in Engineer or Electrical Engineering or equivalent.
6+ years of experience in Physical Design
Synthesis and PNR flows on Multi-Voltage/Low Power designs with greater than 1M instances
Block/Top STA experience, preferably with multiple voltage domains, DFT timing, Timing Constraints debug.
Understanding of Logical Equivalence debug, Low power rule verification, Clock distribution schemes, Timing constraint analysis and feedback to Front-End teams, Static Timing analysis at block/top level.
Experience in scripting using EDA tool API interface for Cadence or Synopsys

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Benefits at Intel

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to

Job Type:
Experienced Hire

Shift:
Shift 1 (United States of America)

Primary Location:
US, California, Folsom

Additional Locations:
US, Arizona, Phoenix, US, California, Santa Clara

Business group:
The Client Engineering group (CEG) is a worldwide organization focused on the development and integration of SOCs, and critical IPs that power Intel's leadership products, driving the Client roadmap for CCG, and invest in future disruptive technologies.

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$139,710.00-$197,230.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.