STA/EMIR IC Sr. Principal Solutions Engineer
Apply NowCompany: Cadence Design Systems
Location: Austin, TX 78745
Description:
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Proficient in Developing STA and EMIR solutions at Full-Chip at Block Level.
(1) Hierarchical STA Flows
(2) Top Block Constraint validation and budgeting
(3) Full chip clock propagation
(4) ETM and power view model generation and validation
(5) Timing and Power Signoff checks to ensure final tapeout quality
(6) PVT Corner selection and margining for Global/Local/Library/Process/Design variations to ensure silicon success
(7) Proficient in scripting for such checks and developing flows for other members to use.
(8) Build regression suite to validate versions and features
We're doing work that matters. Help us solve what others can't.
Proficient in Developing STA and EMIR solutions at Full-Chip at Block Level.
(1) Hierarchical STA Flows
(2) Top Block Constraint validation and budgeting
(3) Full chip clock propagation
(4) ETM and power view model generation and validation
(5) Timing and Power Signoff checks to ensure final tapeout quality
(6) PVT Corner selection and margining for Global/Local/Library/Process/Design variations to ensure silicon success
(7) Proficient in scripting for such checks and developing flows for other members to use.
(8) Build regression suite to validate versions and features
We're doing work that matters. Help us solve what others can't.