Senior Design Verification Engineer
Apply NowCompany: Cynet Systems
Location: Markham, ON L3P 8P3
Description:
Job Description:
Responsibilities:
Responsibilities:
- Maintaining and enhancing verification environment and regression workflow.
- Triaging and debugging regression results.
- nalyzing test plan coverage.
- Writing, modifying, and maintaining test cases and libraries in SystemVerilog/UVM/Ruby.
- Successful candidate should possess the following personal qualities and technical skills (5+ years):
- Experience with SystemVerilog, Verilog and C/C++ is a must.
- Strong understanding of the UVM-based verification methodology.
- Experience with Low Power Verification and debug methodology is a must.
- VCS/DVE familiarity is necessary.
- bility to juggle multiple on-going tasks at a time.
- Strong, independent working ability.
- Strong teamwork and communication skills.
- Good attention to detail and creative thinking ability.