Verification Engineer - Specialized
Apply NowCompany: Cynet Systems
Location: Santa Clara, CA 95051
Description:
Job Description:
Pay Range: $89.28hr - $103.44hr
Responsibilities:
Pay Range: $89.28hr - $103.44hr
Responsibilities:
- Create and implement a verification plan.
- Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design.
- Collaborate with the hardware design team to identify and resolve issues.
- Work in a UVM environment.
- Use of Assertions, and randomized and direct tests.
- Code coverage and debugging.
- nalyze and report on verification results.
- BSEE or CS.
- 10-15 years of solid experience in UVM design verification.
- Strong knowledge of UVM verification, DV tools & methodologies.
- Deep technical background in AISC & SOC verification.
- Experience with CPUs & high speed I/Os.
- Experience with Cadence or Client Verification tools & Verdi.
- Solid experience in System verilog.