Hardware Engineering - Silicon DV Engineer III Silicon DV Engineer III
Apply NowCompany: PRI Global, Inc.
Location: Burlingame, CA 94010
Description:
Job Description: 2 Headcount, Remote
*** Max Hourly BR
What are the top non-negotiable skill sets required for this role?
Power and performance modeling or DV (C, system C, system Verilog, or matlab)
Strong DV background (test plan development, test writing, UVM)
Experience with low power verification (UPF)
Experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flows
Duties:
Responsible for low power verification including both dynamic and static verification
Write and augment existing testplans.
Implement testbench and scoreboards / checkers.
Implement test sequences as per plan and debug failures
Achieve 100% functional, code, and power coverage
Work closely with designers, micro architects & f/w to resolve issues
Ability to communicate & articulate clearly progress / issues with project leads
Must Have Skills:
7+ years of proven experience as a DV engineer
o Implied: Candidate will have hands on Experience with executable test plans and Coverage Driven verification
Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
Experience with UPF based simulation flow
2+ Years of experience with C/C++
Wish List/ Nice to Have:
Power and performance FPGA validation
Hifi4, TIE, CNN, DSP, fixed point, floating point, SONICS, python.
Experience with Power Aware GLS flow
Tcl and Python (or similar) scripting language
ASIC design experience
Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators
Experience with complex SoCs
Knowledge of coverage merging across simulation and formal
MSEE/CS or equivalent experience
Education
Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
Master's Degree preferred but not required
Pursuant to the California Fair Chance Act, Los Angeles County Fair Chance Ordinance for Employers, Los Angeles Fair Chance Initiative for Hiring Ordinance, and San Francisco Fair Chance Ordinance, qualified applicants will be considered for assignment with arrest and conviction records. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness, meet client expectations, standards, and accompanying requirements, and safeguard business operations and company reputation.
Comments for Suppliers:
*** Max Hourly BR
What are the top non-negotiable skill sets required for this role?
Power and performance modeling or DV (C, system C, system Verilog, or matlab)
Strong DV background (test plan development, test writing, UVM)
Experience with low power verification (UPF)
Experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flows
Duties:
Responsible for low power verification including both dynamic and static verification
Write and augment existing testplans.
Implement testbench and scoreboards / checkers.
Implement test sequences as per plan and debug failures
Achieve 100% functional, code, and power coverage
Work closely with designers, micro architects & f/w to resolve issues
Ability to communicate & articulate clearly progress / issues with project leads
Must Have Skills:
7+ years of proven experience as a DV engineer
o Implied: Candidate will have hands on Experience with executable test plans and Coverage Driven verification
Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
Experience with UPF based simulation flow
2+ Years of experience with C/C++
Wish List/ Nice to Have:
Power and performance FPGA validation
Hifi4, TIE, CNN, DSP, fixed point, floating point, SONICS, python.
Experience with Power Aware GLS flow
Tcl and Python (or similar) scripting language
ASIC design experience
Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators
Experience with complex SoCs
Knowledge of coverage merging across simulation and formal
MSEE/CS or equivalent experience
Education
Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
Master's Degree preferred but not required
Pursuant to the California Fair Chance Act, Los Angeles County Fair Chance Ordinance for Employers, Los Angeles Fair Chance Initiative for Hiring Ordinance, and San Francisco Fair Chance Ordinance, qualified applicants will be considered for assignment with arrest and conviction records. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness, meet client expectations, standards, and accompanying requirements, and safeguard business operations and company reputation.
Comments for Suppliers: