Layout Design, Staff Engineer-10699
Apply NowCompany: Synopsys Inc
Location: Sunnyvale, CA 94087
Description:
Descriptions & Requirements
Job Description and Requirements
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
An enthusiastic and detail-oriented Analog & Mixed-Signal (A&MS) Layout Design Engineer eager to make a significant impact in the field of semiconductor design. You have a strong foundation in Electrical Engineering, Computer Science, Physics, or a related discipline, with a keen interest in advanced process nodes and FinFET technology. Your analytical and problem-solving skills are exceptional, and you thrive in collaborative environments, effectively communicating with cross-functional teams. You are familiar with layout techniques, verification methodologies, EDA tools for layout design and verification. As a proactive and independent worker, you are also a team player, ready to engage with senior experts and contribute to innovative IP development.
What You'll Be Doing:
The Impact You Will Have:
What You'll Need:
Who You Are:
A proactive and innovative engineer with a passion for learning, adapting, and contributing to the OTP IP team. You are detail-oriented, with strong problem-solving abilities and excellent communication skills. Your ability to work independently and collaboratively makes you a valuable team member. You are eager to learn, adapt, and contribute to the advancement of semiconductor technology.
The Team You'll Be A Part Of:
You will be part of a dedicated memory team focused on developing IP for customers to integrate into their designs. The team is responsible for the development and implementation of memory solutions, working closely with cross-functional teams to deliver high-quality, reliable IP that meets the demands of the industry.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
Job Description and Requirements
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
An enthusiastic and detail-oriented Analog & Mixed-Signal (A&MS) Layout Design Engineer eager to make a significant impact in the field of semiconductor design. You have a strong foundation in Electrical Engineering, Computer Science, Physics, or a related discipline, with a keen interest in advanced process nodes and FinFET technology. Your analytical and problem-solving skills are exceptional, and you thrive in collaborative environments, effectively communicating with cross-functional teams. You are familiar with layout techniques, verification methodologies, EDA tools for layout design and verification. As a proactive and independent worker, you are also a team player, ready to engage with senior experts and contribute to innovative IP development.
What You'll Be Doing:
- Designing and developing analog and mixed-signal layouts for OTP (One Time Programmable) memory IP in the latest technology nodes.
- Collaborating with cross-functional teams to meet project requirements and deadlines.
- Debugging and resolving a wide range of issues in creative ways.
- Utilizing EDA tools for layout design, verification, and ensuring compliance with DRC, LVS, ERC, and PERC methodologies.
- Working closely with our memory architect to floorplan and develop leading edge memory architecture
- Executing layout projects under the guidance of layout and design leads contributing to memory IP development.
The Impact You Will Have:
- Enhancing the performance and reliability of silicon chips through meticulous layout design.
- Driving innovation in memory IP development, contributing to Synopsys' leadership in the semiconductor industry.
- Improving efficiency and accuracy through automation and advanced verification techniques.
- Contributing to the successful integration of Synopsys IP into customer designs, meeting their specific needs and standards.
- Collaborating with global teams to share knowledge and best practices, fostering a culture of continuous improvement.
What You'll Need:
- Minimum of +10 years of related experience
- Strong analytical and problem-solving skills.
- Excellent communication skills and ability to collaborate with cross-functional teams.
- Understanding of FinFET technology and advanced process nodes.
- Proficient with EDA tools for layout design and verification (DRC, LVS, etc).
- Strong working knowledge of MS Office Suite of applications.
- Familiarity with Python, Tcl, SKILL or other scripting language for layout automation is a plus.
- Proficiency in verbal and written English to collaborate effectively with global teams.
- Ability to work independently while collaborating effectively within a team.
Who You Are:
A proactive and innovative engineer with a passion for learning, adapting, and contributing to the OTP IP team. You are detail-oriented, with strong problem-solving abilities and excellent communication skills. Your ability to work independently and collaboratively makes you a valuable team member. You are eager to learn, adapt, and contribute to the advancement of semiconductor technology.
The Team You'll Be A Part Of:
You will be part of a dedicated memory team focused on developing IP for customers to integrate into their designs. The team is responsible for the development and implementation of memory solutions, working closely with cross-functional teams to deliver high-quality, reliable IP that meets the demands of the industry.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.