Sample Prep Engineer

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Company: Intel

Location: Hillsboro, OR 97124

Description:

Job Details:

Job Description:

Join Intel's Post Silicon Debug Organization as a Sample Prep Engineer, an exciting role where you'll be at the forefront of semiconductor technology.

As a Sample Prep Engineer your responsibilities will include but are not limited to:
  • Responsible for preparing samples of cutting-edge semiconductor devices to support FIB Circuit Editing,
  • Optical Probing, and other debug techniques.
  • Your work will involve both independent and collaborative development projects with Intel experts in the debug field.
  • You will utilize state-of-the-art debug tools and technologies, including CNC, PFIB, LCE, and Dual Beam, among others.
  • Additionally, you will conduct failure analysis of microelectronic devices and publish root-cause reports.
  • Part of your role will also include training junior team members and others.
  • A successful candidate must demonstrate strong problem-solving skills, the ability to work independently and tackle tasks with minimal supervision, and a strong interest in physical debug and fault isolation, with a desire to deeply understand relevant procedures and mechanisms behind various applications and products.


Qualifications:

To be initially considered for this position, you must possess the following minimum qualifications. Preferred qualifications are additional and will be considered a plus factor in identifying top candidates.

Minimum Qualifications:
  • Bachelor's degree in mechanical, electrical, chemical engineering or any STEM related field
  • 1+ years of combined experience in the following areas: integrated circuits and electronics, CAD navigation tools such as Knights or similar tools, failure analysis and machining skills (CNC) and device physics and fabrication process flow.


Preferred Qualifications:
  • Fundamental electronics knowledge, and proficiency in UNIX, PC skills, and Microsoft Office.
  • Demonstrated problem-solving and documentation skills
  • Process documentation
  • Vacuum technology


Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type:
Experienced Hire

Shift:
Shift 2 (United States of America)

Primary Location:
US, Oregon, Hillsboro

Additional Locations:

Business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$104,890.00-$148,080.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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